Manufacturing method of oxide semiconductor device

ABSTRACT

The contact resistance between an oxide semiconductor film and a metal film is reduced. A transistor that uses an oxide semiconductor film and has excellent on-state characteristics is provided. A semiconductor device capable of high-speed operation is provided. In a transistor that uses an oxide semiconductor film, the oxide semiconductor film is subjected to nitrogen plasma treatment. Thus, part of oxygen included in the oxide semiconductor film is replaced with nitrogen, so that an oxynitride region is formed. A metal film is formed in contact with the oxynitride region. The oxynitride region has lower resistance than the other region of the oxide semiconductor film. In addition, the oxynitride region is unlikely to form high-resistance metal oxide at the interface with the contacting metal film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that in this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

2. Description of the Related Art

As materials of semiconductor thin films applicable to transistors, silicon-based semiconductor materials have been widely used, but oxide semiconductors have been attracting attention as alternative materials.

In many cases, transistors that use amorphous silicon, which can be manufactured using the established manufacturing technique, are utilized in display devices; however, the transistors that use amorphous silicon have low field-effect mobility, having difficulty in achieving high definition, low power consumption, and the like of display devices.

Further, the transistors that use amorphous silicon also have a problem of severe electrical characteristic deterioration (low reliability), which occurs with the temperature variation or repetitive operation.

As the integration becomes higher obeying the scaling law and the circuit structure becomes more complex, a problem of an increase in power consumption becomes more significant in semiconductor devices (such as semiconductor memory devices) utilizing transistors that use single crystal silicon and have high field-effect mobility.

Further, it is known that a transistor that uses an oxide semiconductor has a relatively high field-effect mobility compared with a transistor that uses amorphous silicon. An oxide semiconductor can be easily deposited on a large area by a sputtering method or the like, and application of the oxide semiconductor to display devices has been actively examined.

It is pointed out that aluminum oxide having high resistance is produced in the case of directly connecting an oxide semiconductor to an aluminum-based alloy wiring, thereby increasing contact resistance (see Patent Document 1).

Even in the case of using a metal that is relatively unlikely to be oxidized or a metal, an oxide of which has a conducting property, a metal oxide having high resistance is often produced at the interface between the metal and an oxide semiconductor by heat treatment or the like in a later process; accordingly, contact resistance is often increased.

There is a problem in that such high contact resistance between a metal and an oxide semiconductor causes a reduction in on-state characteristics of a transistor.

As a method for reducing the contact resistance, a technique in which a buffer layer having low resistance is provided between an oxide semiconductor and a metal is disclosed. In addition, an oxide semiconductor containing nitrogen, which serves as a buffer layer, is disclosed (see Patent Document 2).

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.     2011-49542 -   [Patent Document 2] Japanese Published Patent Application No.     2011-9724

SUMMARY OF THE INVENTION

The on-state characteristics (e.g., on-state current) of a transistor that uses an oxide semiconductor film are higher than those of a transistor that uses an amorphous silicon film, but are not sufficiently high compared to those of a transistor that uses single crystal silicon.

In some cases, a semiconductor device formed using a transistor that uses single crystal silicon does not need to have such high on-state characteristics of a transistor as to be achieved by using single crystal silicon. In the case where a transistor that uses an oxide semiconductor film is applied to such a semiconductor device, enough performance cannot always be demonstrated due to low on-state characteristics of the transistor.

Specifically, some factors that inhibit carrier transfer may degrade the transistor on-state characteristics to about 30% to 70%, or 10% or less under certain circumstances, of the inherent on-state characteristics of the transistor. One of the factors that inhibit carrier transfer is contact resistance between an oxide semiconductor film and a metal film.

Thus, it is desired that in a transistor that uses an oxide semiconductor film, the contact resistance between an oxide semiconductor film and a metal film, which is a cause for lowering of on-state characteristics, be reduced.

In view of the foregoing, it is an object to reduce contact resistance between an oxide semiconductor film and a metal film.

Further, it is another object to provide a transistor that uses an oxide semiconductor film and has excellent on-state characteristics.

Still another object is to provide a semiconductor device capable of high-speed operation.

A semiconductor device according to an embodiment of the present invention includes an oxide semiconductor film over an insulating surface, a gate insulating film over the oxide semiconductor film, a gate electrode positioned over the gate insulating film and having substantially the same upper surface shape as the gate insulating film, an interlayer insulating film positioned over the oxide semiconductor film and the gate electrode and having an opening reaching part of the oxide semiconductor film, and a wiring positioned over the interlayer insulating film and being in contact with the oxide semiconductor film at the opening in the interlayer insulating film. A region which is in the oxide semiconductor film and is in contact with the wiring is an oxynitride region.

Further, a semiconductor device according to an embodiment of the present invention includes an oxide semiconductor film over an insulating surface, a gate insulating film covering the oxide semiconductor film, a gate electrode overlapping with the oxide semiconductor film with the gate insulating film sandwiched therebetween, an interlayer insulating film positioned over the oxide semiconductor film and the gate electrode and having an opening reaching part of the oxide semiconductor film, and a wiring positioned over the interlayer insulating film and being in contact with the oxide semiconductor film at the opening in the interlayer insulating film. A region which is in the oxide semiconductor film and is in contact with the wiring is an oxynitride region.

In a semiconductor device of an embodiment of the present invention, which has a transistor that uses an oxide semiconductor film, the oxide semiconductor film is subjected to nitrogen plasma treatment to replace part of oxygen included in the oxide semiconductor film with nitrogen and to thereby form an oxynitride region, and a metal film is formed in contact with the oxynitride region.

Note that microwave discharge nitrogen plasma is preferably used in the nitrogen plasma treatment because its damage to the oxide semiconductor film is small and it enables efficient formation of the oxynitride region.

The oxynitride region has a lower resistance than the other region of the oxide semiconductor film. Further, the oxynitride region has a lower oxygen proportion than the oxide semiconductor film right after the deposition; accordingly, a high-resistance metal oxide is unlikely to be formed at the interface with the contacting metal film. As a result, the contact resistance between the oxide semiconductor film and the metal film can be reduced.

Specifically, a semiconductor device according to an embodiment of the present invention is manufactured by forming an oxide semiconductor film over an insulating surface, forming a gate insulating film over the oxide semiconductor film, forming a gate electrode overlapping with the oxide semiconductor film with the gate insulating film sandwiched therebetween; performing treatment which reduces resistance of part of the oxide semiconductor film using the gate electrode as a mask, forming an interlayer insulating film covering the oxide semiconductor film, the gate insulating film and the gate electrode, forming an opening reaching a low-resistance region of the oxide semiconductor film by processing the interlayer insulating film and the gate insulating film, performing nitrogen plasma treatment on an exposed part of the low-resistance region of the oxide semiconductor film, and forming a metal film in contact with the exposed part of the low-resistance region of the oxide semiconductor film.

Note that it is preferable to form metal electrodes in regions that are between the insulating surface and the oxide semiconductor film and do not overlap with the gate electrode. The metal electrodes function as a source electrode and a drain electrode of the transistor.

The thickness of the oxynitride region varies depending on the conditions of the nitrogen plasma treatment or the conditions of the oxide semiconductor film such as the film quality or thickness. Specifically, when the intensity of the nitrogen plasma treatment is low and the thickness of the oxide semiconductor film is large enough, the oxynitride region is formed in a region that is relatively shallow from the vicinity of a surface of the oxide semiconductor film. In contrast, when the intensity of the nitrogen plasma treatment is high and the thickness of the oxide semiconductor film is small (e.g., 5 nm or smaller), the oxynitride region is formed down to an interface between the oxide semiconductor film and the base of the oxide semiconductor film.

In the case where metal electrodes are provided in regions that are between the base of the oxide semiconductor film and the oxide semiconductor film and do not overlap with the gate electrode, it is preferable to form the oxynitride region down to the interface between the oxide semiconductor film and the base in order to reduce the contact resistance.

The oxynitride region formed in the oxide semiconductor film enables a reduction in the contact resistance between the oxide semiconductor film and the metal film.

The reduction of the contact resistance enables provision of a transistor that uses an oxide semiconductor film and has excellent on-state characteristics.

By using the transistor that uses an oxide semiconductor film and has excellent on-state characteristics, a semiconductor device capable of high-speed operation can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1A is a top view and FIGS. 1B and 1C are cross-sectional views illustrating examples of a transistor according to an embodiment of the present invention;

FIGS. 2A to 2C are cross-sectional views illustrating an example of a manufacturing process of a transistor according to an embodiment of the present invention;

FIGS. 3A to 3C are cross-sectional views illustrating an example of a manufacturing process of a transistor according to an embodiment of the present invention;

FIGS. 4A to 4C are cross-sectional views illustrating an example of a manufacturing process of a transistor according to an embodiment of the present invention;

FIGS. 5A to 5C are cross-sectional views illustrating an example of a manufacturing process of a transistor according to an embodiment of the present invention;

FIGS. 6A to 6C are cross-sectional views illustrating an example of a manufacturing process of a transistor according to an embodiment of the present invention;

FIG. 7A is a top view and FIGS. 7B and 7C are cross-sectional views illustrating examples of a transistor according to an embodiment of the present invention;

FIGS. 8A to 8C are cross-sectional views illustrating an example of a manufacturing process of a transistor according to an embodiment of the present invention;

FIG. 9A is a circuit diagram illustrating an example of a semiconductor memory device including a transistor according to an embodiment of the present invention and FIG. 9B shows electrical characteristics;

FIG. 10A is a circuit diagram illustrating an example of a semiconductor memory device including a transistor according to an embodiment of the present invention and FIG. 10B shows electrical characteristics;

FIG. 11A is a block diagram illustrating a specific example of a CPU including a transistor according to an embodiment of the present invention and FIGS. 11B and 11C are circuit diagrams illustrating part of the CPU;

FIGS. 12A to 12D are perspective views each illustrating an example of an electronic device according to an embodiment of the present invention;

FIGS. 13A to 13C are cross-sectional views illustrating a method for making a sample;

FIGS. 14A and 14B are a top view and a cross-sectional view, respectively, of a sample;

FIG. 15 illustrates an example of an apparatus capable of microwave discharge;

FIGS. 16A and 16B are TE images of a cross section of a sample, which are taken with a STEM;

FIGS. 17A and 17B are TE images of a cross section of a sample, which are taken with a STEM; and

FIG. 18 shows XPS spectrum showing a bonding state of a surface of an oxide semiconductor film.

DETAILED DESCRIPTION OF THE INVENTION

(Embodiment 1)

In this embodiment, a transistor which is a semiconductor device according to an embodiment of the present invention and a method for manufacturing the transistor will be described with reference to FIGS. 1A to 1C, FIGS. 2A to 2C, FIGS. 3A to 3C, FIGS. 4A to 4C, FIGS. 5A to 5C, and FIGS. 6A to 6C.

FIG. 1A is a top view and FIGS. 1B and 1C are cross-sectional views of transistors according to an embodiment of the present invention. FIGS. 1B and 1C illustrate cross section A-B taken along dashed-dotted line A-B in the top view of the transistor in FIG. 1A. A gate insulating film 130 in FIG. 1B and a gate insulating film 131 in FIG. 1C have different shapes. For easy understanding, an interlayer insulating film 150, the gate insulating film 130, the gate insulating film 131, and a base insulating film 110 are omitted in FIG. 1A.

The transistor illustrated in FIG. 1B includes the base insulating film 110 over a substrate 100; an oxide semiconductor film 120 over the base insulating film 110; the gate insulating film 130 over the oxide semiconductor film 120; a gate electrode 140 over the gate insulating film 130, which has substantially the same upper surface shape as the gate insulating film 130; the interlayer insulating film 150 over the oxide semiconductor film 120 and the gate electrode 140, which has openings that reach the oxide semiconductor film 120; and a wiring 160 a and a wiring 160 b over the interlayer insulating film 150, which are in contact with the oxide semiconductor film 120 at the openings provided in the interlayer insulating film 150. Note that the base insulating film 110 may be omitted.

The transistor illustrated in FIG. 1C includes the base insulating film 110 over the substrate 100; the oxide semiconductor film 120 over the base insulating film 110; the gate insulating film 131 covering the oxide semiconductor film 120; the gate electrode 140 overlapping with the oxide semiconductor film 120 with the gate insulating film 131 sandwiched therebetween; the interlayer insulating film 150 over the oxide semiconductor film 120 and the gate electrode 140, which has openings that reach the oxide semiconductor film 120; and the wiring 160 a and the wiring 160 b over the interlayer insulating film 150, which are in contact with the oxide semiconductor film 120 at the openings provided in the interlayer insulating film 150. Note that the base insulating film 110 may be omitted.

Here, the oxide semiconductor film 120 includes a low-resistance region 120 a, a low-resistance region 120 b, a high-resistance region 120 c, an oxynitride region 120 d, and an oxynitride region 120 e.

The low-resistance region 120 a and the low-resistance region 120 b are regions including an impurity that reduces the resistance of the oxide semiconductor film. For example, the low-resistance region 120 a and the low-resistance region 120 b are regions including at least one kind of element selected from hydrogen, helium, boron, nitrogen, fluorine, neon, aluminum, phosphorus, argon, arsenic, krypton, indium, tin, antimony, and xenon.

The low resistance of the low-resistance region 120 a and the low-resistance region 120 b can suppress degradation of on-state characteristics of the transistor that uses the oxide semiconductor film 120. For example, the low-resistance region 120 a and the low-resistance region 120 b have a sheet resistance of 30 kΩ/sq or less, preferably 10 kΩ/sq or less, further preferably 1 kΩ/sq or less, and still further preferably 0.7 kΩ/sq or less.

The high-resistance region 120 c is a region having a low concentration of components which are other than main components of the oxide semiconductor film, that is, impurities. For example, the concentrations of respective impurities in the high-resistance region 120 c are each 1×10²⁰ atoms/cm³ or less, preferably 5×10¹⁹ atoms/cm³ or less, and further preferably 1×10¹⁹ atoms/cm³ or less. However, it is difficult to strictly classify components as main components or impurities; therefore, an element included at 1 at. % or more is regarded as a main component in this specification.

The high-resistance region 120 c is a region having a low density of defects. For example, the density of oxygen vacancies in the high-resistance region 120 c is 1×10¹⁶/cm³ or less, preferably 1×10¹⁵/cm³ or less, and further preferably 1×10¹⁴/cm³ or less.

The high-resistance region 120 c has a low concentration of impurities and a low density of defects. In the transistors illustrated in FIGS. 1B and 1C, a channel region is formed in the high-resistance region 120 c, which results in excellent electrical characteristics and high reliability. Further, the off-state currents of the transistors are low. For example, the transistors can have an off-state current of 1×10⁻¹⁸ A or less, preferably 1×10⁻²¹ A or less, and further preferably 1×10⁻²⁴ A or less when having a channel length of 3 μm and a channel width of 1 μm.

The oxynitride region 120 d and the oxynitride region 120 e are regions where part of oxygen included in the oxide semiconductor film has been replaced with nitrogen. For example, the oxynitride region 120 d and the oxynitride region 120 e in the oxide semiconductor film include nitrogen at a concentration of 5 at. % or more, preferably 10 at. % or more, and further preferably 15 at. % or more.

The oxynitride region 120 d and the oxynitride region 120 e have the same thickness as the oxide semiconductor film 120 in FIGS. 1B and 1C; however, the thickness of the oxynitride region 120 d and the oxynitride region 120 e are not limited thereto. For example, the oxynitride region 120 d and the oxynitride region 120 e may be formed only in the vicinity of a surface of the oxide semiconductor film 120 (in a region that is 1 nm to 5 nm deep from the surface of the oxide semiconductor film 120). The oxynitride region 120 d and the oxynitride region 120 e may have a nitrogen concentration gradient in the thickness direction. In that case, the nitrogen concentration on the substrate 100 side is low.

Upper surface shapes of the oxynitride region 120 d and the oxynitride region 120 e are similar to the upper surface shapes of the openings provided in the interlayer insulating film 150. Thus, the wiring 160 a and the wiring 160 b are in contact with the oxynitride region 120 d and the oxynitride region 120 e, respectively, of the oxide semiconductor film 120.

Here, the oxide semiconductor film 120 may be formed using an In—Zn—O compound, a Sn—Zn—O compound, an Al—Zn—O compound, a Zn—Mg—O compound, a Sn—Mg—O compound, an In—Mg—O compound, an In—Ga—O compound, a Sn—Ga—Zn—O compound, an Al—Ga—Zn—O compound, a Sn—Al—Zn—O compound, an In—Sn—Ga—Zn—O compound, an In—Hf—Ga—Zn—O compound, an In—Al—Ga—Zn—O compound, an In—Sn—Al—Zn—O compound, an In—Sn—Hf—Zn—O compound, an In—Hf—Al—Zn—O compound, or an In—Zr—Y—Zn—O compound, for example.

Note that an “In—Zn—O compound” refers to an oxide including In and Zn as its main components and there is no particular limitation on the atomic ratio of In and Zn.

The oxide semiconductor film 120 is preferably formed using an In-M-Zn—O compound. Here, M refers to Ga, Al, Sn, Hf, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Ni, Ti, Y, or Zr. It is preferable to use an In-M-Zn—O compound where M is Ga or Sn.

M is preferably an element having a higher bonding energy with oxygen than In and Zn. In that case, since M having a higher bonding energy with oxygen is included, oxygen vacancies are less likely to be caused in the oxide semiconductor film.

It is preferable to use an In-M-Zn—O compound having a composition ratio equal to or closer to In:M:Zn=3:1:2 [atomic ratio] because, in that case, field-effect mobility of the transistor can be high.

The oxide semiconductor film 120 can be in a single crystal state, a polycrystalline (also referred to as polycrystal) state, an amorphous state, or the like.

The oxide semiconductor film 120 is preferably a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film.

The CAAC-OS film is not completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film with a crystal-amorphous mixed phase structure where crystal parts (or crystal regions) and amorphous parts (or amorphous regions) are included in an amorphous phase. Note that in most cases, the crystal part fits inside a cube whose one side is less than 100 nm. From an observation image obtained with a transmission electron microscope (TEM), a boundary between an amorphous part and a crystal part in the CAAC-OS film is not clear. Further, with the TEM, a grain boundary in the CAAC-OS film is not found. Thus, in the CAAC-OS film, a reduction in electron mobility, due to the grain boundary, is suppressed.

In each of the crystal parts included in the CAAC-OS film, a c-axis is aligned in a direction parallel to a normal vector of a surface on which the CAAC-OS film is formed or a normal vector of a surface of the CAAC-OS film, triangular or hexagonal atomic arrangement which is seen from the direction perpendicular to the a-b plane is formed, and metal atoms are arranged in a layered manner or metal atoms and oxygen atoms are arranged in a layered manner when seen from the direction perpendicular to the c-axis. Note that, among crystal parts, the directions of the a-axis and the b-axis of one crystal part may be different from those of another crystal part. In this specification, a simple term “perpendicular” includes a range from 85° to 95°. In addition, a simple term “parallel” includes a range from −5° to 5°.

In the CAAC-OS film, distribution of crystal parts is not necessarily uniform. For example, in the formation process of the CAAC-OS film, in the case where crystal growth occurs from a surface side of the oxide semiconductor film, the proportion of crystal parts in the vicinity of the surface of the oxide semiconductor film is higher than that in the vicinity of the surface on which the oxide semiconductor layer is formed in some cases. Further, when an impurity is added to the CAAC-OS film, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

Since the c-axes of the crystal parts included in the CAAC-OS film are aligned in the direction parallel to a normal vector of a surface on which the CAAC-OS film is formed or a normal vector of a surface of the CAAC-OS film, the directions of the c-axes may be different from each other depending on the shape of the CAAC-OS film (the cross-sectional shape of the surface on which the CAAC-OS film is formed or the cross-sectional shape of the surface of the CAAC-OS film). Note that when the CAAC-OS film is formed, the direction of c-axis of the crystal part is the direction parallel to a normal vector of the surface on which the CAAC-OS film is formed or a normal vector of the surface of the CAAC-OS film. The crystal part is formed by film formation or by performing treatment for crystallization such as heat treatment after film formation.

With use of the CAAC-OS film in a transistor, change in electric characteristics of the transistor due to irradiation with visible light or ultraviolet light can be reduced. Thus, the transistor has high reliability.

There is no particular limitation on the substrate 100 as long as it has heat resistance enough to withstand at least heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, or a sapphire substrate may be used as the substrate 100. Further alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, an SOI (silicon on insulator) substrate, or the like may be used. It is preferable to use any of these substrates provided with a semiconductor element as the substrate 100.

Further alternatively, a flexible substrate may be used as the substrate 100. Note that as a method for forming a transistor over a flexible substrate, there is a method in which, after a transistor is formed over a non-flexible substrate, the transistor is separated from the non-flexible substrate and transferred to the substrate 100 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor.

The base insulating film 110 may be formed to have a single-layer structure or a stacked-layer structure including at least one of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, cesium oxide, tantalum oxide, and magnesium oxide.

It is preferable that the base insulating film 110 be sufficiently flat. Specifically, the film serving as a base is provided so as to have an average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, further preferably 0.1 nm or less. When Ra is less than or equal to the above value, a crystal region is easily formed in the oxide semiconductor film 120. Note that Ra is obtained by expanding, into three dimensions, arithmetic mean surface roughness that is defined by JIS B 0601: 2001 (ISO4287:1997) so as to be able to apply it to a curved surface. Ra can be expressed as an “average value of the absolute values of deviations from a reference surface to a designated surface” and is defined by Formula 1.

$\begin{matrix} {{Ra} = \left. {\frac{1}{S_{0}}{\int_{y\; 1}^{y\; 2}\int_{x\; 1}^{x\; 2}}} \middle| {{f\left( {x,y} \right)} - Z_{0}} \middle| \ {{\mathbb{d}x}\ {\mathbb{d}y}} \right.} & \left\lbrack {{FORMULA}\mspace{14mu} 1} \right\rbrack \end{matrix}$

Here, the specific surface is a surface which is a target of roughness measurement, and is a quadrilateral region which is specified by four points represented by the coordinates (x₁, y₁, f(x₁, y₁)), (x₁, y₂, f(x₁, y₂)), (x₂, y₁, f(x₂, y₁)), and (x₂, y₂, f(x₂, y₂)). Moreover, S₀ represents the area of a rectangle which is obtained by projecting the specific surface on the xy plane, and Z₀ represents the height of the reference surface (the average height of the specific surface). Ra can be measured using an atomic force microscope (AFM).

Silicon oxynitride refers to a substance that contains more oxygen than nitrogen and, for example, includes oxygen, nitrogen, silicon, and hydrogen at concentrations higher than or equal to 50 at. % and lower than or equal to 70 at. %, higher than or equal to 0.5 at. % and lower than or equal to 15 at. %, higher than or equal to 25 at. % and lower than or equal to 35 at. %, and higher than or equal to 0 at. % and lower than or equal to 10 at. %, respectively. Further, silicon nitride oxide refers to a substance that contains more nitrogen than oxygen and, for example, contains oxygen, nitrogen, silicon, and hydrogen at concentrations higher than or equal to 5 at. % and lower than or equal to 30 at. %, higher than or equal to 20 at. % and lower than or equal to 55 at. %, higher than or equal to 25 at. % and lower than or equal to 35 at. %, and higher than or equal to 10 at. % and lower than or equal to 25 at. %, respectively. Note that percentages of oxygen, nitrogen, silicon, and hydrogen fall within the aforementioned ranges in the case where measurement is performed using Rutherford backscattering spectrometry (RBS) or hydrogen forward scattering (HFS). In addition, the total of the percentages of the constituent elements does not exceed 100 at. %.

It is preferable that an insulating film from which oxygen is released by heat treatment be used as the base insulating film 110.

“To release oxygen by heat treatment” means that the amount of released oxygen is greater than or equal to 1.0×10¹⁸ atoms/cm³, or greater than or equal to 3.0×10²⁰ atoms/cm³ in TDS on an oxygen atom basis.

Here, a method for measuring the amount of released oxygen using TDS will be described.

The total amount of released gas from a measurement sample in TDS is proportional to the integral value of the ion intensity of the released gas. Then, this integral value is compared with the reference value of a reference sample, whereby the total amount of released gas can be calculated.

For example, the number of released oxygen molecules (N_(O2)) from a measurement sample can be calculated according to Formula 2 using the TDS results of a silicon wafer containing hydrogen at a predetermined density, which is the reference sample, and the TDS results of the measurement sample. Here, all gasses having a mass number of 32 which are obtained by the TDS are assumed to originate from an oxygen molecule. CH₃OH can be given as a gas having a mass number of 32, but is not taken into consideration on the assumption that CH₃OH is unlikely to be present. Further, an oxygen molecule including an oxygen atom having a mass number of 17 or 18, which is an isotope of an oxygen atom, is also not taken into consideration because the proportion of such a molecule in the natural world is minimal.

$\begin{matrix} {N_{O\; 2} = {\frac{N_{H\; 2}}{S_{H\; 2}} \times S_{O\; 2} \times \alpha}} & \left\lbrack {{FORMULA}\mspace{14mu} 2} \right\rbrack \end{matrix}$

N_(H2) is the value obtained by conversion of the number of hydrogen molecules released from the reference sample into density. S_(H2) is the integral value of ion intensity when the reference sample is analyzed by TDS. Here, the reference value of the reference sample is expressed by N_(H2)/S_(H2). S_(O2) is the integral value of ion intensity when the measurement sample is analyzed by TDS. α is a coefficient affecting the ion intensity in the TDS. For details of Formula 2, Japanese Published Patent Application No. H6-275697 is referred to. Note that the amount of released oxygen was measured with a thermal desorption spectroscopy apparatus produced by ESCO Ltd., EMD-WA1000S/W using a silicon wafer containing hydrogen atoms at 1×10¹⁶ atoms/cm³ as the reference sample.

Further, in the TDS, part of oxygen is detected as an oxygen atom. The ratio between oxygen molecules and oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that, since the above α includes the ionization rate of oxygen molecules, the number of released oxygen atoms can be estimated through the evaluation of the number of the released oxygen molecules.

Note that N_(O2) is the number of released oxygen molecules. When the number of released oxygen molecules is converted into the number of released oxygen atoms, the number of released oxygen atoms is twice the number of released oxygen molecules.

The supply of oxygen from the base insulating film 110 to the oxide semiconductor film 120 can reduce the interface state density at the interface between the oxide semiconductor film 120 and the base insulating film 110. As a result, carrier trapping at the interface between the oxide semiconductor film 120 and the base insulating film 110 due to the operation of a transistor or the like can be suppressed, and thus, a highly reliable transistor can be obtained.

Further, in some cases, electric charge is generated due to oxygen vacancies in the oxide semiconductor film 120. In general, some oxygen vacancies in the oxide semiconductor film 120 serve as donors and cause release of electrons which are carriers. Consequently, the threshold voltage of a transistor shifts in the negative direction. When oxygen is sufficiently supplied from the base insulating film 110 to the oxide semiconductor film 120 and the oxide semiconductor film 120 preferably contains excessive oxygen, the density of oxygen vacancies in the oxide semiconductor film 120, which cause the negative shift of the threshold voltage, can be reduced.

The gate insulating film 130 and the gate insulating film 131 can be formed using a method and a material similar to those of the base insulating film 110.

The gate electrodes 140 can be formed to have a single-layer structure or a stacked-layer structure including at least one of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta, and W, a nitride of any of these elements, an oxide of any of these elements, and an alloy of any of these elements. Alternatively, an oxide or an oxynitride which contains at least In and Zn may be used. For example, an In—Ga—Zn—O—N compound or the like may be used.

The interlayer insulating film 150 is formed using a method and a material similar to those of the base insulating film 110.

It is preferable that the interlayer insulating film 150 have low relative permittivity and a sufficient thickness. For example, a silicon oxide film having a relative permittivity of approximately 3.8 and a thickness of greater than or equal to 300 nm and less than or equal to 1000 nm may be used. A surface of the interlayer insulating film 150 has a little charge because of the influence of atmospheric components and the like, which might cause the shift of the threshold voltage of the transistor. Therefore, it is preferable that the interlayer insulating film 150 have relative permittivity and a thickness such that the influence of the charge at the surface is sufficiently reduced. For the same reason, a resin film may be formed over the interlayer insulating film 150 to reduce the influence of the charge at the surface.

The wiring 160 a and the wiring 160 b can be formed using a method and a material similar to those of the gate electrode 140. Note that the wiring 160 a and the wiring 160 b may be formed in the same layer.

The wiring 160 a and the wiring 160 b are in contact with the oxynitride region 120 d and the oxynitride region 120 e, respectively, of the oxide semiconductor film 120. This contact suppresses generation of another layer (e.g., an oxide of the material of the wiring 160 a and the wiring 160 b) at the contact interface, thereby reducing the contact resistance.

Next, a method for manufacturing the transistor illustrated in FIG. 1B will be described with reference to FIGS. 2A to 2C, FIGS. 3A to 3C, FIGS. 4A to 4C, and FIGS. 5A to 5C.

First, the base insulating film 110 is formed over the substrate 100 (see FIG. 2A). The base insulating film 110 can be formed by a chemical vapor deposition (CVD) method, a sputtering method, a molecular beam epitaxy (MBE) method, or a pulsed laser deposition (PLD) method and is preferably formed by a sputtering method. Note that depending on the material of the substrate 100, it is not necessary to provide the base insulating film 110.

Next, an oxide semiconductor film 121 is formed (see FIG. 2B). The oxide semiconductor film 121 may be formed by a CVD method, a sputtering method, an MBE method, or a PLD method and is preferably formed by a sputtering method.

In the case where the oxide semiconductor film 121 is a CAAC-OS film, the oxide semiconductor film 121 may be formed by a sputtering method using a polycrystalline oxide semiconductor sputtering target, for example. By collision of ions with the sputtering target, a crystal region included in the sputtering target may be separated from the target along an a-b plane; in other words, a sputtered particle having a plane parallel to an a-b plane (flat-plate-like sputtered particle or pellet-like sputtered particle) may flake off from the sputtering target. In that case, the flat-plate-like sputtered particle reaches a substrate while maintaining the crystal state, whereby the CAAC-OS film can be formed.

As an example of the sputtering target, an In—Ga—Zn—O compound target will be described below.

The In—Ga—Zn—O compound target, which is polycrystalline, is made by mixing InO_(x) powder, GaO_(y) powder, and ZnO_(z) powder in a predetermined molar ratio, applying pressure, and performing heat treatment at a temperature higher than or equal to 1000° C. and lower than or equal to 1500° C. Note that X, Y, and Z are each a given positive number. Here, the predetermined molar ratio of InO_(X) powder to GaO_(Y) powder and ZnO_(Z) powder is, for example, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. The kinds of powder and the molar ratio for mixing powder may be determined as appropriate depending on the desired sputtering target.

For the formation of the CAAC-OS film, the following conditions are preferably used.

By reducing the amount of impurities entering the CAAC-OS film during the formation thereof, the crystal state can be prevented from being broken by the impurities. For example, the concentration of impurities (e.g., hydrogen, water, carbon dioxide, or nitrogen) which exist in the deposition chamber may be reduced. Furthermore, the concentration of impurities in a deposition gas may be reduced. Specifically, a deposition gas whose dew point is −80° C. or lower, preferably −100° C. or lower is used.

By increasing the substrate heating temperature during the deposition, migration of a sputtered particle is likely to occur after the sputtered particle reaches a substrate. Specifically, the substrate heating temperature during the deposition is higher than or equal to 100° C. and lower than or equal to 740° C., preferably higher than or equal to 200° C. and lower than or equal to 500° C. By increasing the substrate heating temperature during the deposition, when the flat-plate-like sputtered particle reaches the substrate, migration occurs on the substrate, so that a flat plane of the flat-plate-like sputtered particle is attached to the substrate.

Furthermore, it is preferable that the proportion of oxygen in the deposition gas be increased and the power be optimized in order to reduce plasma damage at the deposition. The proportion of oxygen in the deposition gas is 30 vol. % or higher, preferably 100 vol. %. In the above-described manner, the oxide semiconductor film 121 which is a CAAC-OS film can be formed.

Next, first heat treatment is preferably performed. By the first heat treatment, the degree of crystallinity of the oxide semiconductor film 121 is increased and/or the concentration of impurities in the oxide semiconductor film 121 can be reduced so that the density of defects can be reduced.

The first heat treatment may be performed in an atmosphere selected from an oxidizing atmosphere, an inert atmosphere, a reduced-pressure atmosphere, and a dry-air atmosphere or in a combined atmosphere of two or more of the aforementioned atmospheres. Preferably, heat treatment is performed in an inert atmosphere or a reduced-pressure atmosphere and then heat treatment is further performed in an oxidizing atmosphere or a dry-air atmosphere. The first heat treatment may be performed at a temperature higher than or equal to 150° C. and lower than or equal to 650° C., preferably higher than or equal to 250° C. and lower than or equal to 500° C., and further preferably higher than or equal to 300° C. and lower than or equal to 450° C. A resistance heating method, a lamp heating method, a method using a heated gas, or the like may be used in the first heat treatment.

Note that an oxidizing atmosphere refers to an atmosphere containing an oxidizing gas. The oxidizing gas is oxygen, ozone, nitrous oxide, or the like, and it is preferable that the oxidizing gas do not contain water, hydrogen, and the like. For example, the purity of oxygen, ozone, or nitrous oxide introduced into a heat treatment apparatus is 8 N (99.999999%) or higher, preferably 9 N (99.9999999%) or higher. As the oxidizing atmosphere, an oxidizing gas mixed with an inert gas may be used. In that case, the mixture contains an oxidizing gas at a concentration at least higher than or equal to 10 ppm. By performing heat treatment in an oxidizing atmosphere, the density of oxygen vacancies in the oxide semiconductor film 121 can be reduced.

Further, an inert atmosphere refers to an atmosphere containing an inert gas such as nitrogen or a rare gas as the main component. Specifically, the concentration of a reactive gas such as an oxidizing gas in an inert atmosphere is lower than 10 ppm. By performing heat treatment in an inert atmosphere, the concentration of impurities included in the oxide semiconductor film 121 can be reduced.

A reduced-pressure atmosphere refers to an atmosphere with a pressure of a treatment chamber of lower than or equal to 10 Pa. By performing heat treatment in a reduced-pressure atmosphere, the concentration of impurities included in the oxide semiconductor film 121 can become low as compared to the case of employing the inert atmosphere.

The dry-air atmosphere refers to an atmosphere with a dew point of lower than or equal to −40° C., preferably lower than or equal to −50° C. and with an oxygen content of approximately 20% and a nitrogen content of approximately 80%. The dry-air atmosphere is a kind of oxidizing atmosphere. Since the dry-air atmosphere is relatively low in cost, it is suitable for mass production.

Next, the oxide semiconductor film 121 is processed, so that an oxide semiconductor film 122 is formed (see FIG. 2C). Note that the term “processing” means performing etching treatment using a resist mask that is formed by a photolithography method to obtain a film having a desired shape.

Next, a gate insulating film 131 is formed (see FIG. 3A). The gate insulating film 131 may be formed by a CVD method, a sputtering method, an MBE method, or a PLD method and is preferably formed by a sputtering method.

Next, a conductive film 141 is formed (see FIG. 3B). The conductive film 141 may be formed by a CVD method, a sputtering method, an MBE method, or a PLD method and is preferably formed by a sputtering method.

Then, the conductive film 141 is processed, so that the gate electrode 140 is formed (see FIG. 3C).

Next, the gate insulating film 131 is processed to have an upper surface shape that is similar to that of the gate electrode 140, so that a gate insulating film 130 is formed (see FIG. 4A). For the processing of the gate insulating film 130, the gate electrode 140 or the resist mask that is used for processing the gate electrode 140 may be used.

Next, using the gate electrode 140 as a mask, impurities that reduce the resistance of the oxide semiconductor film 122 are added to the oxide semiconductor film 122, so that a low-resistance region 122 a and a low-resistance region 122 b are formed (see FIG. 4B). Note that a region to which the impurities that reduce the resistance of the oxide semiconductor film are not added is a high-resistance region 122 c.

As the added impurities that reduce the resistance of the oxide semiconductor film, one or more of hydrogen, helium, boron, nitrogen, fluorine, neon, aluminum, phosphorus, argon, arsenic, krypton, indium, tin, antimony, and xenon may be used. The method for adding the impurities may be an ion implantation method or an ion doping method. Alternatively, plasma treatment or heat treatment in an atmosphere including the impurities that reduce the resistance of the oxide semiconductor film may be employed. Preferably, an ion implantation method is used. Further alternatively, after adding the impurities that reduce the resistance of the oxide semiconductor film by an ion implantation method, heat treatment may be performed in an inert atmosphere or a reduced-pressure atmosphere.

Next, an interlayer insulating film 151 is formed (see FIG. 4C). The interlayer insulating film 151 may be formed by a CVD method, a sputtering method, an MBE method, a PLD method, or a spin coating method and is preferably formed by a CVD method or a sputtering method.

Next, the interlayer insulating film 151 is processed, so that the interlayer insulating film 150 having openings which reach the low-resistance region 122 a and the low-resistance region 122 b is formed (see FIG. 5A).

Next, treatment using microwave discharge nitrogen plasma 170 is performed (see FIG. 5B). The treatment using the microwave discharge nitrogen plasma 170 may be performed with any apparatus that is capable of microwave discharge without limitation to a particular apparatus; for example, a CVD apparatus or an etching apparatus may be used. Specifically, the treatment using the microwave discharge nitrogen plasma 170 may be performed in an atmosphere including nitrogen or including nitrogen and argon at a pressure of higher than or equal to 1 Pa and lower than or equal to 1000 Pa, preferably higher than or equal to 1 Pa and lower than or equal to 100 Pa, at a temperature of a stage over which a substrate is set of higher than or equal to room temperature and lower than or equal to 600° C., preferably higher than or equal to 300° C. and lower than or equal to 450° C., and at a power of greater than or equal to 100 W and less than or equal to 10000 W, preferably greater than or equal to 2000 W and less than or equal to 4000 W. The frequency of the microwave may be higher than or equal to 2 GHz and lower than or equal to 4 GHz, and may be 2.45 GHz, for example.

In this embodiment, the treatment is performed using the microwave discharge nitrogen plasma; however, the treatment is not limited thereto. For example, nitrogen plasma treatment that can replace part of oxygen included in the oxide semiconductor film with nitrogen may be employed.

By the above-described treatment using the microwave discharge nitrogen plasma 170, the oxynitride region 120 d and the oxynitride region 120 e can be formed in part of the oxide semiconductor film 120 (see FIG. 5C). The oxide semiconductor film 120 further includes the low-resistance region 120 a, the low-resistance region 120 b, and the high-resistance region 120 c. The low-resistance region 120 a and the low-resistance region 120 b refer to the low-resistance region 122 a and the low-resistance region 122 b in which the oxynitride region 120 d and the oxynitride region 120 e are formed. Note that different reference numerals are assigned to the high-resistance region 120 c and the high-resistance region 122 c for convenience; however, the high-resistance region 120 c and the high-resistance region 122 c have the same composition ratio and shape.

Next, the wiring 160 a and the wiring 160 b are formed; thus, the transistor illustrated in FIG. 1B is completed. The obtained transistor may be covered by a resin.

Similarly, a method for manufacturing the transistor illustrated in FIG. 1C will be described with reference to FIGS. 2A to 2C, FIGS. 3A to 3C, and FIGS. 6A to 6C.

Since the method for manufacturing the transistor in the steps illustrated in FIGS. 2A to 2C and FIGS. 3A to 3C is the same as that in the case of the transistor illustrated in FIG. 1B, description of the steps is omitted.

After the gate electrode 140 is formed as illustrated in FIG. 3C, impurities that reduce the resistance of the oxide semiconductor film 122 are added to the oxide semiconductor film 122, so that the low-resistance region 122 a and the low-resistance region 122 b are formed (see FIG. 6A). Note that a region to which the impurities that reduce the resistance of the oxide semiconductor film are not added is a high-resistance region 122 c.

Next, the interlayer insulating film 150 is formed, and then the treatment using the microwave discharge nitrogen plasma 170 is performed (see FIG. 6B).

By the above-described treatment using the microwave discharge nitrogen plasma 170, the oxynitride region 120 d and the oxynitride region 120 e can be formed in the oxide semiconductor film 120 (see FIG. 6C). In addition, the oxide semiconductor film 120 further includes the low-resistance region 120 a, the low-resistance region 120 b, and the high-resistance region 120 c.

Next, the wiring 160 a and the wiring 160 b are formed; thus, the transistor illustrated in FIG. 1C is completed. The obtained transistor may be covered by a resin.

In the above-described manner, the contact resistance between an oxide semiconductor film and a metal film can be reduced. The low contact resistance between the oxide semiconductor film and the metal film enables provision of a transistor that uses an oxide semiconductor film and has excellent on-state characteristics.

This embodiment can be implemented in appropriate combination with any of the other embodiments or examples.

(Embodiment 2)

In this embodiment, transistors having structures different from those of the transistors in Embodiment 1 and a method for manufacturing the transistors will be described with reference to FIGS. 7A to 7C and FIGS. 8A to 8C.

FIG. 7A is a top view and FIGS. 7B and 7C are cross-sectional views of transistors which are semiconductor devices according to an embodiment of the present invention. FIGS. 7B and 7C illustrate cross section A-B taken along dashed-dotted line A-B in the top view of the transistor in FIG. 7A. The gate insulating film 130 in FIG. 7B and the gate insulating film 131 in FIG. 7C have different shapes. For easy understanding, the interlayer insulating film 150, the gate insulating film 130, the gate insulating film 131, an electrode 180 a, an electrode 180 b, and a base insulating film 111 are omitted in FIG. 7A.

The transistor illustrated in FIG. 7B includes the base insulating film 111 having depressions, over the substrate 100; the electrode 180 a and the electrode 180 b provided in the depressions of the base insulating film 111, an oxide semiconductor film 120 over the base insulating film 111, the electrode 180 a, and the electrode 180 b; the gate insulating film 130 over the oxide semiconductor film 120; the gate electrode 140 over the gate insulating film 130, which has substantially the same top surface shape as the gate insulating film 130; the interlayer insulating film 150 over the oxide semiconductor film 120 and the gate electrode 140, which has openings that reach the oxide semiconductor film 120; and the wiring 160 a and the wiring 160 b over the interlayer insulating film 150, which are in contact with the oxide semiconductor film 120 at the openings provided in the interlayer insulating film 150.

The transistor illustrated in FIG. 7C includes the base insulating film 111 having depressions, over the substrate 100; the electrode 180 a and the electrode 180 b provided in the depressions of the base insulating film 111, the oxide semiconductor film 120 over the base insulating film 111, the electrode 180 a, and the electrode 180 b; the gate insulating film 131 covering the oxide semiconductor film 120; the gate electrode 140 overlapping with the oxide semiconductor film 120 with the gate insulating film 131 sandwiched therebetween; the interlayer insulating film 150 over the oxide semiconductor film 120 and the gate electrode 140, which has openings that reach the oxide semiconductor film 120; and the wiring 160 a and the wiring 160 b over the interlayer insulating film 150, which are in contact with the oxide semiconductor film 120 at the openings provided in the interlayer insulating film 150.

The electrode 180 a and the electrode 180 b can be formed using a method and a material similar to those of the gate electrode 140. Note that the electrode 180 a and the electrode 180 b may be formed in the same layer.

The depth of the depression provided in the base insulating film 111 is set to be substantially the same as the thickness of the electrode 180 a and the electrode 180 b. In this manner, the oxide semiconductor film 120 that is formed over the base insulating film 111, the electrode 180 a, and the electrode 180 b can be formed on a flat surface. Note that the depth of the depression provided in the base insulating film 111 may be different from the thickness of the electrode 180 a and the electrode 180 b.

By providing the electrode 180 a and the electrode 180 b, the contact area of the electrodes is increased as compared to the cases of the transistors described in Embodiment 1; thus, on-state characteristics of the transistors in this embodiment can be further improved.

Next, a method for manufacturing the transistors illustrated in FIGS. 7B and 7C will be described with reference to FIGS. 2A to 2C, FIGS. 3A to 3C, FIGS. 4A to 4C, FIGS. 5A to 5C, FIGS. 6A to 6C, and FIGS. 8A to 8C.

The transistors described in this embodiment are different from the transistors described in Embodiment 1 in that the base insulating film 111, the electrode 180 a, and the electrode 180 b are provided.

Therefore, description of Embodiment 1 can be referred to for part of the method for manufacturing the transistors in this embodiment.

FIGS. 8A to 8C illustrate a method for forming the base insulating film 111, the electrode 180 a, and the electrode 180 b.

First, the base insulating film 110 is formed over the substrate 100 (see FIG. 2A).

Next, the base insulating film 110 is processed to form the base insulating film 111 having depressions (see FIG. 8A).

Next, a conductive film 180 is formed (see FIG. 8B). The conductive film 180 may be formed by a CVD method, a sputtering method, an MBE method, or a PLD method and is preferably formed by a sputtering method.

Next, the conductive film 180 is processed to form the electrode 180 a and the electrode 180 b (see FIG. 8C). The processing of the conductive film 180 may be performed by CMP (chemical mechanical polishing) treatment. By the CMP treatment, an uppermost surface of the base insulating film 111 can be substantially at the same level as the uppermost surfaces of the electrode 180 a and the electrode 180 b.

Note that the method for processing the conductive film 180 to form the electrode 180 a and the electrode 180 b is not limited to the CMP treatment. For example, the electrode 180 a and the electrode 180 b may be formed in such a manner that a planarization film is formed over the conductive film 180, and part of the planarization film and part of the conductive film 180 are etched until a projection of the base insulating film 111 is exposed. In such a case, the etching of the planarization film and the conductive film 180 is preferably performed under conditions in which the etching rate of the planarization film is substantially the same as that of the conductive film 180.

For the later process of the manufacturing method, Embodiment 1 can be referred to.

By providing the electrode 180 a and the electrode 180 b, the transistor can operate, for example, even in the case where an opening penetrating the oxide semiconductor film 122 is formed at the time of forming the interlayer insulating film 150 (at the time of forming the openings). Accordingly, yield of the transistor can be increased.

In the above-described manner, the contact resistance between an oxide semiconductor film and a metal film can be reduced. The low contact resistance enables provision of a transistor that uses an oxide semiconductor film and has excellent on-state characteristics.

This embodiment can be implemented in appropriate combination with any of the other embodiments or examples.

(Embodiment 3)

In this embodiment, an example of manufacturing a semiconductor memory device using any of the transistors described in Embodiment 1 and 2 will be described.

Typical examples of a volatile semiconductor memory device include a dynamic random access memory (DRAM) which stores data by selecting a transistor included in a memory element and accumulating an electric charge in a capacitor, and a static random access memory (SRAM) which holds stored data using a circuit such as a flip-flop.

Typical examples of a nonvolatile semiconductor memory device include a flash memory which has a node between a gate electrode and a channel region of a transistor and stores data by holding an electric charge in the node.

Any of the transistors described in Embodiment 1 and 2 can be applied to some of transistors included in the above-described semiconductor memory device.

First, a memory cell included in a semiconductor memory device to which any of the transistors described in Embodiment 1 and 2 is applied will be described with reference to FIGS. 9A and 9B.

The memory cell includes a transistor Tr and a capacitor C. One of a source and a drain of the transistor Tr is connected to a bit line BL, a gate of the transistor Tr is connected to a word line WL, the other of the source and the drain of the transistor Tr is connected to the capacitor C, and the bit line BL is connected to a sense amplifier SAmp (see FIG. 9A).

Note that it is known that the voltage held in the capacitor C is gradually decreased with time as shown in FIG. 9B owing to the off-state current of the transistor Tr. A voltage originally charged from V0 to V1 is decreased with time to VA that is a limit for reading out data 1. This period is called a holding period T_1. In the case of a two-level memory cell, refresh operation needs to be performed within the holding period T_1.

Here, when any of the transistors described in Embodiment 1 and 2 is used as the transistor Tr, the holding period T_1 can be increased because off-state current is small. That is, frequency of the refresh operation can be reduced; thus, power consumption can be reduced. For example, in the case of applying a transistor including an oxide semiconductor film in which an off-state current is less than or equal to 1×10⁻²¹ A, preferably less than or equal to 1×10⁻²⁴ A, a memory cell that can hold data for several days to several decades without supply of electric power can be formed.

As described above, according to one embodiment of the present invention, a semiconductor memory device with high reliability and low power consumption can be provided.

By applying any of the transistors having excellent on-state characteristics described in Embodiment 1 and 2, it is possible to provide a semiconductor memory device capable of high-speed operation, in which charge can be quickly accumulated in the capacitor C.

Next, a memory cell included in a semiconductor memory device to which any of the transistors described in Embodiment 1 and 2 is applied will be described with reference to FIGS. 10A and 10B.

FIG. 10A is a circuit diagram of a memory cell. The memory cell includes a transistor Tr_1, a transistor Tr_2, and a capacitor C. A gate of the transistor Tr_1 is connected to a word line WL_1, and a source of the transistor Tr_1 is connected to a source line SL_1. A source of the transistor Tr_2 is connected to a source line SL_2, and a drain of the transistor Tr_2 is connected to a drain line DL_2. One terminal of the capacitor C is connected to a capacitor line CL. The other terminal of the capacitor C, a drain of the transistor Tr_1, and a gate of the transistor Tr_2 are connected to each other through a node N.

The memory cell utilizes variation in the nominal threshold voltage of the transistor Tr_2, which is caused corresponding to the potential of the node N. For example, FIG. 10B shows a relation between a voltage V_(CL) of the capacitor line CL and a drain current I_(d) _(—) 2 flowing through the transistor Tr_2.

Here, the voltage of the node N can be adjusted through the transistor Tr_1. For example, the potential of the source line SL_1 is set to VDD. In this case, when the potential of the word line WL_1 is set to be higher than or equal to a potential obtained by adding VDD to the threshold voltage Vth of the transistor Tr_1, the potential of the node N can be HIGH. Further, when the potential of the word line WL_1 is set to be lower than or equal to the threshold voltage Vth of the transistor Tr_1, the potential of the node N can be LOW.

Thus, either a V_(CL)-I_(d) _(—) 2 curve (N=LOW) or a V_(CL)-I_(d) _(—) 2 curve (N=HIGH) can be obtained. That is, when N=LOW, I_(d) _(—) 2 is small at a V_(CL) of 0V; accordingly, data 0 is stored. Further, when N=HIGH, I_(d) _(—) 2 is large at a V_(CL) of 0V; accordingly, data 1 is stored. In such a manner, data can be stored.

Here, when any of the transistors described in Embodiment 1 and 2 is used as the transistor Tr_1, the off-state current of the transistor can be significantly reduced; therefore, unintentional leakage of an electric charge accumulated in the node N by flowing between the source and the drain of the transistor Tr_1 can be suppressed. As a result, data can be held for a long time. Further, since the threshold voltage of the transistor Tr_1 according to one embodiment of the present invention is controlled, a voltage needed for writing can be reduced; thus, power consumption can be made small compared to a flash memory or the like.

Note that any of the transistors described in Embodiment 1 and 2 may be used as the transistor Tr_2. The transistor has excellent on-state characteristics. Accordingly, a semiconductor memory device including the transistor can operate at high speed.

As described above, according to one embodiment of the present invention, a semiconductor memory device with high reliability for a long time, low power consumption and high degree of integration can be obtained.

This embodiment can be implemented in appropriate combination with any of the other embodiments or examples.

(Embodiment 4)

A central processing unit (CPU) can be formed using any of the transistors described in Embodiment 1 and 2 or the semiconductor memory device described in Embodiment 3 for at least part of the CPU.

FIG. 11A is a block diagram illustrating a specific structure of the CPU. The CPU illustrated in FIG. 11A includes an arithmetic logic unit (ALU) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface (Bus I/F) 1198, a rewritable ROM 1199, and a ROM interface (ROM I/F) 1189 over a substrate 1190. A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190. The ROM 1199 and the ROM interface 1189 may be provided over a separate chip. Obviously, the CPU shown in FIG. 11A is just an example in which the configuration has been simplified, and an actual CPU may have various configurations depending on the application.

An instruction that is input to the CPU through the bus interface 1198 is input to the instruction decoder 1193 and decoded therein, and then, input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. While the CPU is executing a program, the interrupt controller 1194 judges an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller 1197 generates an address of the register 1196, and reads/writes data from/to the register 1196 in accordance with the state of the CPU.

The timing controller 1195 generates signals for controlling operation timings of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generator for generating an internal clock signal CLK2 based on a reference clock signal CLK1, and supplies the clock signal CLK2 to the above circuits.

In the CPU illustrated in FIG. 11A, a memory element is provided in the register 1196. As the memory element in the register 1196, for example, the semiconductor memory device described in Embodiment 3 can be used.

In the CPU illustrated in FIG. 11A, the register controller 1197 selects operation of retaining data in the register 1196 in accordance with an instruction from the ALU 1191. That is, the register controller 1197 selects whether data is retained by a flip-flop or a capacitor in the memory element included in the register 1196. When data is retained by the flip-flop, a power supply voltage is supplied to the memory element in the register 1196. When data is retained by the capacitor, the data in the capacitor is rewritten, and supply of the power supply voltage to the memory element in the register 1196 can be stopped.

A switching element provided between a memory element group and a node to which a power supply potential VDD or a power supply potential VSS is supplied, as illustrated in FIG. 11B or FIG. 11C, allows the power supply voltage to be stopped. Circuits illustrated in FIGS. 11B and 11C will be described below.

FIGS. 11B and 11C each illustrate an example of a structure including any of the transistors described in Embodiment 1 and 2 as a switching element for controlling supply of a power supply potential to a memory element.

The memory device illustrated in FIG. 11B includes a switching element 1141 and a memory element group 1143 including a plurality of memory elements 1142. Specifically, as each of the memory elements 1142, the memory element described in Embodiment 3 can be used. Each of the memory elements 1142 included in the memory element group 1143 is supplied with the high-level power supply potential VDD through the switching element 1141. Further, each of the memory elements 1142 included in the memory element group 1143 is supplied with a potential of a signal IN and a potential of the low-level power supply potential VSS.

In FIG. 11B, as the switching element 1141, a transistor in which a semiconductor with a wide band gap such as an oxide semiconductor is used for an active layer is used, and the switching of the transistor is controlled by a signal Sig A supplied to a gate electrode thereof.

Note that FIG. 11B illustrates the structure in which the switching element 1141 includes only one transistor; however, without limitation thereon, the switching element 1141 may include a plurality of transistors. In the case where the switching element 1141 includes a plurality of transistors which serves as switching elements, the plurality of transistors may be connected to each other in parallel, in series, or in combination of parallel connection and series connection.

In FIG. 11C, an example of a memory device in which each of the memory elements 1142 included in the memory element group 1143 is supplied with the low-level power supply potential VSS through the switching element 1141 is illustrated. The supply of the low-level power supply potential VSS to each of the memory elements 1142 included in the memory element group 1143 can be controlled by the switching element 1141.

When a switching element is provided between a memory element group and a node to which the power supply potential VDD or the power supply potential VSS is supplied, data can be retained even in the case where an operation of a CPU is temporarily stopped and the supply of the power supply voltage is stopped; accordingly, power consumption can be reduced. For example, while a user of a personal computer does not input data to an input device such as a keyboard, the operation of the CPU can be stopped, so that the power consumption can be reduced.

Although the CPU is given as an example, the transistor and the semiconductor memory device can also be applied to an LSI such as a digital signal processor (DSP), a custom LSI, or a field programmable gate array (FPGA).

This embodiment can be implemented in appropriate combination with any of the other embodiments or examples.

(Embodiment 5)

In this embodiment, examples of an electronic device including at least one of the transistors, the semiconductor memory device, and the CPU described in Embodiments 1 to 4 will be described.

FIG. 12A illustrates a portable information terminal. The portable information terminal illustrated in FIG. 12A includes a housing 9300, a button 9301, a microphone 9302, a display portion 9303, a speaker 9304, and a camera 9305, and has a function as a mobile phone.

FIG. 12B illustrates a display. The display illustrated in FIG. 12B includes a housing 9310 and a display portion 9311.

FIG. 12C illustrates a digital still camera. The digital still camera illustrated in FIG. 12C includes a housing 9320, a button 9321, a microphone 9322, and a display portion 9323.

FIG. 12D illustrates a double-foldable portable information terminal. The double-foldable portable information terminal illustrated in FIG. 12D includes a housing 9630, a display portion 9631 a, a display portion 9631 b , a hinge 9633, and an operation switch 9638.

Part or whole of the display portion 9631 a and/or the display portion 9631 b can function as a touch panel. By touching an operation key displayed on the touch panel, a user can input data, for example.

By application of one embodiment of the present invention, the performance of an electronic device can be improved and the reliability of the electronic device can be improved.

This embodiment can be implemented in appropriate combination with any of the other embodiments.

EXAMPLE 1

In this example, the contact resistance between an oxide semiconductor film and a metal film was measured.

A method for making a measurement sample will be described below with reference to FIGS. 13A to 13C and FIGS. 14A and 14B.

First, a silicon oxide film 210 was formed over a glass substrate 200. The silicon oxide film 210 was formed with a thickness of 300 nm by a sputtering method.

Then, an In—Ga—Zn—O film, which is an oxide semiconductor film, was formed. The In—Ga—Zn—O film was formed with a thickness of 50 nm by a sputtering method using an In—Ga—Zn—O target (In:Ga:Zn=3:1:2 in an atomic ratio).

Next, the In—Ga—Zn—O film was processed into an island-shaped In—Ga—Zn—O film.

Then, a silicon oxynitride film 231 was formed. The silicon oxynitride film was formed with a thickness of 10 nm by a CVD method.

Then, phosphorus ions were added to the In—Ga—Zn—O film through the silicon oxynitride film 231 to reduce the resistance of the island-shaped In—Ga—Zn—O film; thus, an In—Ga—Zn—O film 222 was formed (see FIG. 13A). The addition of phosphorus ions was conducted with an ion implantation apparatus with an acceleration voltage of 30 kV and a dose of 1×10¹⁵ ions/cm².

Next, a silicon oxynitride film was formed. The silicon oxynitride film was formed with a thickness of 300 nm by a CVD method. Then, the silicon oxynitride film and the silicon oxynitride film 231 were processed, so that a silicon oxynitride film 250 and a silicon oxynitride film 230 which have openings (e.g., an opening 290) that reach the In—Ga—Zn—O film 222 were formed. Here, the opening 290 has an upper surface shape of 2 μm×2 μm.

Next, treatment using microwave discharge nitrogen plasma 270 was performed (see FIG. 13B), so that the In—Ga—Zn—O film 222 was formed into an In—Ga—Zn—O film 220 including a low-resistance region 220 a and an oxynitride region 220 b. The treatment using the microwave discharge nitrogen plasma 270 was performed for 180 seconds under the following conditions: the flow rates of argon and nitrogen were 1000 sccm and 500 sccm respectively, the pressure was 6 Pa, the temperature of a sample stage was 450° C., and an electric power of 3000 W (2.45 GHz) was applied to an antenna electrode.

The treatment using the microwave discharge nitrogen plasma 270 was performed with an apparatus illustrated in FIG. 15. The apparatus illustrated in FIG. 15 includes a supply port that supplies a gas from the outside of the apparatus, a sample stage on which a sample is set, a quartz plate that functions as a slow wave plate, and an antenna electrode that is covered with the quartz plate and receives a microwave.

Next, a metal film was formed and processed into a metal film including a measurement pad 260 a, a measurement pad 260 b, a measurement pad 260 c, and a measurement pad 260 d. In this manner, a sample was made (see FIG. 14A and FIG. 14B). Note that as the metal film, a stacked-layer film in which a titanium film with a thickness of 50 nm, an aluminum film with a thickness of 100 nm, and a titanium film with a thickness of 50 nm were stacked, was used.

A cross section A-B in FIG. 14B is taken along dashed-dotted line A-B in the top view of FIG. 14A.

Next, heat treatment was performed on the sample in a clean room atmosphere at 300° C. for 1 hour.

A method for measuring contact resistance R_(C) between the metal film and the In—Ga—Zn—O film in the sample will be described below with reference to FIG. 14A.

A current flowing between the measurement pad 260 c and the measurement pad 260 a was measured under a condition where a voltage between the measurement pad 260 d and the measurement pad 260 b was 0.25 V. The contact resistance R_(C) is the value obtained by dividing 0.25 V by the measured current value.

A sample whose manufacturing method and structure are similar to those of the sample described in this example except that the treatment using the microwave discharge nitrogen plasma 270 was not performed was separately made. The contact resistance R_(C) of the separately-made sample was 564.6Ω. Further, the contact resistance R_(C) of the sample made in this example with the treatment using the microwave discharge nitrogen plasma 270 was 172.2Ω. Note that the above-mentioned contact resistance R_(C) is the average value among five samples made under the same conditions.

The above shows that the microwave discharge nitrogen plasma treatment performed on the In—Ga—Zn—O film, which is an oxide semiconductor film, enables the contact resistance between the In—Ga—Zn—O film and the metal film to be reduced.

EXAMPLE 2

In this example, the bonding state of the surface after performing microwave discharge nitrogen plasma treatment on an oxide semiconductor film was evaluated.

A sample was made in the following manner.

First, a silicon oxide film was formed over a glass substrate. The silicon oxide film was formed with a thickness of 300 nm by a sputtering method.

Next, an In—Ga—Zn—O film, which is an oxide semiconductor film, was formed. The In—Ga—Zn—O film was formed with a thickness of 10 nm by a sputtering method using an In—Ga—Zn—O target (In:Ga:Zn=3:1:2 in an atomic ratio).

Next, microwave discharge nitrogen plasma treatment was performed on the In—Ga—Zn—O film. The microwave discharge nitrogen plasma treatment was performed for 180 seconds under the following conditions: the flow rates of argon and nitrogen were 1000 sccm and 200 sccm respectively, the pressure was 100 Pa, the temperature of a sample stage was 350° C., and an electric power of 3000 W (2.45 GHz) was applied to an antenna electrode.

Bonding states of the surfaces of the sample made in the above-described manner and a reference sample made in a similar method except that the microwave discharge nitrogen plasma treatment was not performed were evaluated by X-ray photoelectron spectroscopy (XPS). FIG. 18 shows XPS spectra of the samples.

In FIG. 18, the spectrum indicated by triangle symbols represents the reference sample, while the spectrum indicated by circular symbols represents the sample made in this example.

Focusing on the binding energy around 397 eV that indicates metal-N bonding in FIG. 18, substantially no peak is observed for the reference sample, while a sharp peak is observed for the sample made in this example.

The above shows that the microwave discharge nitrogen plasma treatment on the oxide semiconductor film causes bonding between nitrogen and part of metal.

EXAMPLE 3

In this example, how the microwave discharge nitrogen plasma treatment affects the state of the interface between the oxide semiconductor film and the metal film was evaluated.

A sample was made in the following manner.

First, a silicon oxide film 301 was formed over a glass substrate 300. The silicon oxide film 301 was formed with a thickness of 330 nm by a sputtering method.

Then, a surface of the silicon oxide film 301 was polished by 30 nm by CMP treatment so as to be flat.

Next, an In—Ga—Zn—O film, which is an oxide semiconductor film, was formed. The In—Ga—Zn—O film was formed with a thickness of 30 nm by a sputtering method using an In—Ga—Zn—O target (In:Ga:Zn=3:1:2 in an atomic ratio).

Next, heat treatment was performed at 450° C. in a nitrogen atmosphere for 1 hour, and then heat treatment was further performed at 450° C. in an oxygen atmosphere for 1 hour.

Next, the In—Ga—Zn—O film was processed into an island-shaped In—Ga—Zn—O film.

Then, a silicon oxynitride film was formed. The silicon oxynitride film was formed with a thickness of 20 nm by a CVD method.

Then, boron ions were added into the In—Ga—Zn—O film through the silicon oxynitride film to reduce the resistance of the island-shaped In—Ga—Zn—O film; thus, an In—Ga—Zn—O film 302 was formed. The addition of boron ions was conducted with an ion implantation apparatus with an acceleration voltage of 15 kV and a dose of 1×10¹⁵ ions/cm².

Next, a silicon oxynitride film was formed. The silicon oxynitride film was formed with a thickness of 300 nm by a CVD method. In this manner, a silicon oxide film 303 in which the silicon oxide film with a thickness of 20 nm and the silicon oxide film with a thickness of 300 nm were stacked was formed.

Then, openings that reach the In—Ga—Zn—O film 302 were provided in the silicon oxide film 303.

Next, microwave discharge nitrogen plasma treatment was performed on an exposed region of the In—Ga—Zn—O film 302. The microwave discharge nitrogen plasma treatment was performed for 180 seconds under the following conditions: the flow rates of argon and nitrogen were 1000 sccm and 200 sccm respectively, the pressure was 40 Pa, the temperature of a sample stage was 300° C., and an electric power of 2000 W (2.45 GHz) was applied to an antenna electrode.

Next, an aluminum alloy film including a slight amount of nickel and a slight amount of lanthanum was formed. The aluminum alloy film was formed with a thickness of 300 nm by a sputtering method.

Then, a metal film 304 was formed by processing the aluminum alloy film.

Next, heat treatment was performed on the sample at 300° C. in a clean room atmosphere for 1 hour.

Cross-sectional shapes of the sample made in the above-described manner and a reference sample made in a similar method except that the microwave discharge nitrogen plasma treatment was not performed were observed with a scanning transmission electron microscope (STEM).

Here, FIGS. 16A and 16B show phase contrast images (also referred to as transmitted electron images or TE images) of a cross-sectional shape of the reference sample. Note that FIG. 16B is an enlarged view showing the vicinity of the interface between the In—Ga—Zn—O film 302 and the metal film 304 in FIG. 16A.

Similarly, FIGS. 17A and 17B show TE images of a cross-sectional shape of the sample made in this example. Note that FIG. 17B is an enlarged view showing the vicinity of the interface between the In—Ga—Zn—O film 312 and the metal film 304 in FIG. 17A.

In FIG. 16B, a layer that is not the In—Ga—Zn—O film 302 or the metal film 304 (another layer) with a thickness of several nanometers is formed at the interface between the In—Ga—Zn—O film 302 and the metal film 304.

In FIG. 17B, such another layer is not formed at the interface between the In—Ga—Zn—O film 312 and the metal film 304.

The above shows that by performing microwave discharge nitrogen plasma treatment on the oxide semiconductor film before formation of the metal film, such another layer is less likely to be generated at the interface between the oxide semiconductor film and the metal film.

This application is based on Japanese Patent Application serial no. 2011-199652 filed with Japan Patent Office on Sep. 13, 2011, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A manufacturing method of a semiconductor device, comprising the steps of: forming an oxide semiconductor film on an insulating surface; forming a gate insulating film over the oxide semiconductor film; forming a gate electrode over the gate insulating film; forming an interlayer insulating film covering the oxide semiconductor film, the gate insulating film, and the gate electrode; forming an opening in the interlayer insulating film reaching the oxide semiconductor film; performing nitrogen plasma treatment on the oxide semiconductor film through the opening in the interlayer insulating film; and forming a metal film in the opening and over the interlayer insulating film.
 2. The manufacturing method of the semiconductor device according to claim 1, wherein the nitrogen plasma treatment is microwave discharge nitrogen plasma treatment.
 3. The manufacturing method of the semiconductor device according to claim 1, wherein the oxide semiconductor film comprises a crystalline region having a c-axis aligned in a direction perpendicular to a surface of the oxide semiconductor film.
 4. The manufacturing method of the semiconductor device according to claim 1, wherein the oxide semiconductor film comprises at least one element selected from In, Ga, Sn, and Zn.
 5. The manufacturing method of the semiconductor device according to claim 1, wherein the nitrogen plasma treatment is performed at a temperature of 300° C. or higher.
 6. The manufacturing method of the semiconductor device according to claim 1, further comprising the step of reducing a resistance of part of the oxide semiconductor film to form a low-resistance region after the step of forming the gate electrode.
 7. The manufacturing method of the semiconductor device according to claim 6, wherein the low-resistance region comprises at least one kind of element selected from hydrogen, helium, boron, nitrogen, fluorine, neon, aluminum, phosphorus, argon, arsenic, krypton, indium, tin, antimony, and xenon.
 8. The manufacturing method of the semiconductor device according to claim 6, wherein a sheet resistance in the low-resistance region is reduced to be 30 kΩ/sq or less.
 9. A manufacturing method of a semiconductor device, comprising the steps of: forming a source electrode and a drain electrode on an insulating surface; forming an oxide semiconductor film over the source electrode and the drain electrode; forming a gate insulating film over the oxide semiconductor film; forming a gate electrode over the gate insulating film; reducing a resistance of part of the oxide semiconductor film to form a low-resistance region; forming an interlayer insulating film covering the oxide semiconductor film, the gate insulating film, and the gate electrode; forming an opening in the interlayer insulating film reaching the oxide semiconductor film; performing nitrogen plasma treatment on the oxide semiconductor film through the opening in the interlayer insulating film; and forming a metal film in the opening and over the interlayer insulating film.
 10. The manufacturing method of the semiconductor device according to claim 9, wherein the nitrogen plasma treatment is microwave discharge nitrogen plasma treatment.
 11. The manufacturing method of the semiconductor device according to claim 9, wherein the oxide semiconductor film comprises a crystalline region having a c-axis aligned in a direction perpendicular to a surface of the oxide semiconductor film.
 12. The manufacturing method of the semiconductor device according to claim 9, wherein the oxide semiconductor film comprises at least one element selected from In, Ga, Sn, and Zn.
 13. The manufacturing method of the semiconductor device according to claim 9, wherein the low-resistance region comprises at least one kind of element selected from hydrogen, helium, boron, nitrogen, fluorine, neon, aluminum, phosphorus, argon, arsenic, krypton, indium, tin, antimony, and xenon.
 14. The manufacturing method of the semiconductor device according to claim 9, wherein a sheet resistance in the low-resistance region is reduced to be 30 kΩ/sq or less.
 15. The manufacturing method of the semiconductor device according to claim 9, wherein the nitrogen plasma treatment is performed at a temperature of 300° C. or higher.
 16. The manufacturing method of the semiconductor device according to claim 9, wherein the source electrode and the drain electrode are formed by planarizing a conductive film on an insulating film with depressions so that the source electrode and the drain electrode are formed in the depressions. 